Asynchronous arbiter with bounded resolution time and predictable output state

摘要

An arbiter circuit ( 100 ) can include a latch ( 106 ) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn 1 and latn 2 ). A filter section ( 108 ) can prevent metastable states of latch output signals (latn 1 and latn 2 ) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit ( 110 ) can activate a feedback signal (fb) after a predetermined delay (delta), provided both output signals (Sel_A and Sel_B) remain inactive.