发明名称 |
Memory controller with staggered request signal output |
摘要 |
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
|
申请公布号 |
US2007086268(A1) |
申请公布日期 |
2007.04.19 |
申请号 |
US20050252957 |
申请日期 |
2005.10.17 |
申请人 |
SHAETFER IAN P;STOTT BRET;LAU BENEDICT C |
发明人 |
SHAETFER IAN P.;STOTT BRET;LAU BENEDICT C. |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|