发明名称 Semiconductor memory device
摘要 According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.
申请公布号 US9368210(B2) 申请公布日期 2016.06.14
申请号 US201514741869 申请日期 2015.06.17
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Maejima Hiroshi;Hosono Koji
分类号 G11C11/34;G11C16/04;G11C16/10;G11C16/06;G11C16/08;G11C16/34;H01L27/088;H01L27/115;G11C16/26;H01L21/8234 主分类号 G11C11/34
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory device comprising: a plurality of memory strings, each including a string of memory cells and a first selection transistor connected to a first end of the string; a row decoder including a first transistor, a first terminal of the first transistor being coupled to a gate of the first selection transistor; and a first driver including a second transistor, a third transistor, and a first level shifter, both a first terminal of the second transistor and a first terminal of the third transistor being coupled to a second terminal of the first transistor, an output of the first level shifter being coupled to a gate of the second transistor, each of the second and third transistors being a first high-withstand-voltage type transistor, a first negative voltage being capable of being applied to a back gate of the third transistor.
地址 Minato-ku JP