Custom chaining stubs for instruction code translation

摘要

A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.

主权项

1. A method of executing instruction code in a processing system comprising a microprocessor comprising a hardware decoder, the method comprising:
translating instruction code in a form non-native to the microprocessor into a translated instruction set native to the microprocessor using a translator, wherein the translated instruction set comprises a branch instruction with a target address external to the translation; connecting the branch instruction to a chaining stub operable to selectively allow additional instruction code at the target address to be directly received and decoded in a hardware decoder, wherein the hardware decoder is operable to decode instruction code for execution in the microprocessor; executing the translated instruction set until the chaining stub is reached; and decoding and executing the additional instruction code at the target address using the hardware decoder.