发明名称 Speculative finish of instruction execution in a processor core
摘要 In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.
申请公布号 US9389867(B2) 申请公布日期 2016.07.12
申请号 US201514840997 申请日期 2015.08.31
申请人 International Business Machines Corporation 发明人 Chadha Sundeep;Lloyd Bryan;Nguyen Dung Q.;Ray David S.;Stolt Benjamin W.
分类号 G06F9/38 主分类号 G06F9/38
代理机构 Russell Ng PLLC 代理人 Russell Ng PLLC ;Bennett Steven L.
主权项 1. A method of data processing, comprising: tracking high latency operations of a processor core in entries of a data structure associated with an execution unit of a processor core; in the execution unit, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishing execution of an instruction dependent on the high latency operation, wherein the speculatively finishing includes reporting an identifier of the entry to completion logic of the processor core and freeing a resource in an execution pipeline of the execution unit utilized by the instruction; the completion logic recording a dependence of the instruction on the high latency operation and committing an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation; and in response to unsuccessful completion of the high latency operation: the completion logic flushing the instruction without committing the execution result to the architected state; andthe processor core reissuing the instruction with an indication that speculative finishing of the instruction is inhibited.
地址 Armonk NY US