Encoding a data address using XOR operation wherein address bits are transformed by multiple preset polynomials

摘要

The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand.

主权项

1. A method for encoding a data address, comprising:
receiving an uncoded address; performing an exclusive-OR operation on one or more bits of the uncoded address by using multiple preset transform polynomials, wherein the multiple preset transform polynomials correspond to multiple bits of an encoded address on a one-to-one basis; and obtaining the encoded address according to a result of the exclusive-OR operation, wherein when the uncoded address is 17 bits, the multiple preset transform polynomials comprise: out16=in9^in11^in13^in14^in15^in16; out15=in8^in10^in12^in13^in14^in15; out14=in7^in9^in11^in12^in13^in14; out13=in6^in8^in10^in11^in12^in13; out12=in5^in7^in9^in10^in11^in12; out11=in4^in6^in8^in9^in10^in11; out10=in3^in5^in7^in8^in9^in10; out9=in2^in4^in6^in7^in8^in9; out8=in1^in3^in5^in6^in7^in8; out7=in0^in2^in4^in5^in6^in7; out6=in1^in3^in4^in5^in6^in9^in11^in13^in14^in15^in16; out5=in0^in2^in3^in4^in5^in8^in10^in12^in13^in14^in15; out4=in1^in2^in3^in4^in7^in12^in15^in16; out3=in0^in1^in2^in3^in6^in11^in14^in15; out2=in0^in1^in2^in5^in9^in10^in11^in15^in16; out1=in0^in1^in4^in6^in8^in10^in11^in13^in16, and out0=in0^in3^in7^in10^in11^in13^in14^in16, wherein, out I indicates an output value of an Ith bit, a value of the I ranges from 0 to 16, in J indicates an input value of a Jth bit, and a value of the J ranges from 0 to 16.