发明名称 |
Method of controlling parallel processing at an instruction level and processor for realizing the method |
摘要 |
Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction buffer, an instruction register unit for storing and issuing the sent instructions to a plurality of execution units in the order of instruction, and a judgement part for judging whether it is possible to execute a set of unissued instructions to be next issued, in parallel, as stored in the instruction buffer and/or the instruction register unit and for controlling parallel processing of the set of instructions, based on the result of a judgement on the possibility of parallel processing.
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申请公布号 |
US5894582(A) |
申请公布日期 |
1999.04.13 |
申请号 |
US19960596628 |
申请日期 |
1996.02.05 |
申请人 |
HITACHI, LTD. |
发明人 |
YOSHIDA, SHOJI;HOTTA, TAKASHI;TANAKA, SHIGEYA |
分类号 |
G06F9/38;(IPC1-7):G06F9/28 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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