| 摘要 |
A clock signal generator (1) for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop (3) adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop (3) in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter (11) arranged to generate an inverse of the output signal and a multiplexer unit (12) arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.
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