SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

摘要

The present invention discloses a shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, and comprising first to third N-type transistors, and gates of the first, second N-type transistors respectively receive gate voltages of n−2th, n−2th pixels, and first end of the first, second N-type transistors respectively receive first and second input signals, and both second ends of the first and second N-type transistors are coupled to a gate of the third N-type transistor; the gate voltages of the n−2th, n−2th pixels are respectively employed to control on-off of the first and second N-type transistors, and to make the first input signal on-off the third N-type transistor; n is a nature number larger than 2; a first end of the third N-type transistor is coupled to a first or second clock signal, and a second end is employed as being a voltage output end to be coupled to the nth pixel. The present invention can diminish the dimension of the frame of liquid crystal display. The present invention also provides a gate driving circuit and a liquid crystal display.

主权项

1. A shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, wherein the shift register unit comprises a first N-type transistor, a second N-type transistor, and a third N-type transistor, wherein,
a gate of the first N-type transistor receives a gate voltage of a n−2th pixel, and a first end of the first N-type transistor receives a first input signal, and a second end of the first N-type transistor is coupled to a gate of the third N-type transistor; wherein the gate voltage of the n−2th pixel is employed to control on-off of the first N-type transistor, and to control on-off of the first input signal to the third N-type transistor; wherein n is a nature number larger than 2; a gate of the second N-type transistor receives a gate voltage of a n+2th pixel, and a first end of the second N-type transistor receives a second input signal, and a second end of the second N-type transistor is coupled to the gate of the third N-type transistor; wherein the gate voltage of the n+2th pixel is employed to control on-off of the second N-type transistor, and to control on-off of the second input signal to the third N-type transistor; a first end of the third N-type transistor is coupled to a first or second clock signal, and a second end of the third N-type transistor is employed as being a voltage output end of the shift register unit to be coupled to the nth pixel for charging and discharging the nth pixel, and to provide a gate voltage.