| 摘要 |
<p>A programmable logic array (PLA) is described, having an integral decoder (14) for selecting individual product lines (P1-P7). The integral decoder receives an input address by way of a set of buffers (c), which can be disabled so as to disable the integral decoder in normal operation. The buffers can be tested in their disabled state by means of an extra product line and extra output line (27). The extra product line (26) is coupled to all the bit lines and to the extra output line, but not to any of the other output lines; the extra output line is coupled to the extra product line, but not to any of the other product lines. The buffers are tested by applying a sequence of addresses to the buffers in their disabled state, and observing the extra output line.</p> |
