A wideband signal processing receiver system (200) including an interface (204) for connecting to an analogue to digital converter (ADC) (112) of a broader signal chain lineup; wherein the interface (204) receives digital data from the ADC (112); a field programmable gate array (FPGA) (206) and associated configuration for converting the digital data into two digital signal paths; the two digital signal paths consisting of a frequency domain path (222) and an optionally decimated time domain path (220); and a memory and/or for storing or transferring high speed bus/link data from the frequency domain path (222) and the time domain path (220). P222102/P222102_10786219_1 C:) 22 I C) ONQ
