发明名称 A general purpose, reconfigurable system for processing serial bit streams
摘要 Disclosed is a system (106) for testing serial communications electrical circuit boards (102) which interfaces to a board being tested through a plurality of serial channels (110, 112). The system contains a plurality of personality modules (204), each of which can interface directly to a channel. A personality module (204) will perform level shifting, data encoding/decoding, line termination, and clock/framing extraction as needed for a particular serial protocol. The system (106) also contains one or more reconfigurable bit processors (402, 404, 406, 408) which may be connected together in a building block fashion to perform low-level processing on serial data received from or sent to a personality module (204). One of a plurality of serial test sequencers (410, 412) receives or sends data from/to a reconfigurable bit processor (402, 404, 406, 408); provides a user programmable means to control the application and reception of test patterns to and from a channel; and interfaces to the user through a system controller (108). <IMAGE>
申请公布号 EP0475631(B1) 申请公布日期 1996.10.09
申请号 EP19910307848 申请日期 1991.08.28
申请人 HEWLETT-PACKARD COMPANY 发明人 MCAULIFFE, ROBERT E.;CAIN, CHRISTOPHER B.;SIEFERS, JOHN E.
分类号 G01R31/317;G01R31/319;(IPC1-7):G06F11/26;H04M3/24 主分类号 G01R31/317
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