Boundaries adjustment in linearly addressable, physical memory, whereby first and second memory segments are respectively associated with all cache-capable and not cache-capable logical memory areas

摘要

The same linearly addressable, physical memory is addressed according to the amount of cache-capable logical memory areas within two memory segments (S1 and S2). The first memory segment (S1) is respectively associated with all cache-capable logical memory areas, and the second memory segment (S2) with all not cache-capable logical memory areas. The method involves setting the boundaries of at least one cache-capable logical memory area within a linearly addressable, physical memory of a microprocessor which comprises a segmentally adjustable, internal data cache. The same linearly addressable, physical memory is addressed according to the amount of cache-capable logical memory areas within two memory segments (S1 and S2). The first memory segment (S1) is respectively associated with all cache-capable logical memory areas, and the second memory segment (S2) with all not cache-capable logical memory areas. The memory segments are associated with different memory area offsets. The address decoding for access on memory cells of the physical memory from the logical memory areas of the memory segments results incompletely, in such way, that each address of each logical memory area of the memory segments points respectively on a memory place of the physical memory.