DELAY CIRCUIT AND DELAY LOCK LOOP DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a device for realizing low jitter and a small area of a DLL (delay lock loop).

SOLUTION: This device is provided with: a first delay circuit series having a plurality of stages of delay units 101 to 110; a second delay circuit series having a plurality of stages of delay units 111 to 121; and a plurality of transfer circuits 131 to 141 provided corresponding to each step of the first delay circuit series and controlling the transfer of an output of each stage of the first delay circuit series to a corresponding stage of the second delay circuit series on the basis of each inputted control signal. The delay units 101 to 110 of each stage of the first delay circuit series inversely output an input signal. Delay units of each stage of the second delay circuit series includes a logic circuit for inputting an output of the transfer circuits corresponding to the delay units and an output of delay units of a preceding stage of the delay units and outputting an output signal to a post stage, and independently selects a propagation path of a leading edge and trailing edge of an inputted signal to thereby make a duty factor variable.

COPYRIGHT: (C)2005,JPO&NCIPI