| 摘要 |
Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered. |
| 主权项 |
1. A method for handling a modulated signal for a wireless device, the method comprising:
receiving a clock signal; generating a first sync enable signal and a second sync enable signal based on an even edge of the clock signal, wherein the generating of the first sync enable signal comprise:
generating, by a first D Flip-Flop (DFF), a divided clock signal based on the clock signal;generating, by a second DFF, a first output signal based on the divided clock signal from the first DFF;generating, by a third DFF, a second output signal based on the divided clock signal and the first output signal from the second DFF; andgenerating, by a fourth DFF, the first sync enable signal based on the clock signal and the second output signal from the third DFF; generating, by a first divider having a first initial operating condition, a first IQ path comprising a first I component signal and a first Q component signal based on the first sync enable signal; receiving, by the first divider from a control circuit, a first enable signal, wherein the first divider only generates the first IQ path when it receives the first enable signal and the first sync enable signal; powering the first divider after receiving the first sync enable signal; generating, by a second divider having a second initial operating condition, a second IQ path comprising a second I component signal and a second Q component signal based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered; receiving, by the second divider from a control circuit, a second enable signal, wherein the second divider only generates the second IQ path when it receives the second enable signal and the second sync enable signal; and powering the second divider after receiving the second sync enable signal. |
