Configuring Power Management Functionality In A Processor

摘要

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

主权项

1. A system on a chip (SoC) comprising:
a plurality of cores formed on a single semiconductor die, a core of the plurality of cores to execute one or more threads; the core of the plurality of cores comprising a fetch unit to fetch instructions from the instruction cache, a decode unit to decode the instructions and a plurality of execution units to perform out-of-order execution of the instructions; one or more control registers to store a first indication that two or more cores of the plurality of cores are to operate at independent performance states; a plurality of voltage regulators formed on the single semiconductor die, a voltage regulator of the plurality of voltage regulators associated with one of the plurality of cores; a power controller formed on the single semiconductor die, the power controller to control the plurality of voltage regulators to provide a voltage and/or frequency to a first core of the plurality of cores independently of a voltage and/or frequency to one or more other cores and to determine whether to update the voltage and/or frequency of the first core based on a workload of the first core, thermal constraints, and activity counters; and at least one additional voltage regulator formed on the single semiconductor die and associated with processor circuitry external to the plurality of cores, the at least one additional voltage regulator to allow the processor circuitry external to the cores to operate at a different voltage and/or frequency than one or more cores of the plurality of cores; and an integrated memory controller to communicatively couple the plurality of cores to a dynamic random access system memory.