发明名称 MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
摘要 A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
申请公布号 US2016181265(A1) 申请公布日期 2016.06.23
申请号 US201514854542 申请日期 2015.09.15
申请人 STMicroelectronics (Rousset) SAS 发明人 Regnier Arnaud;Mirabel Jean-Michel;Niel Stephan;La Rosa Francesco
分类号 H01L27/115;H01L29/78;H01L29/788;G11C16/14;G11C16/04 主分类号 H01L27/115
代理机构 代理人
主权项 1. A memory cell, comprising: a selection gate extending vertically in a trench made in a semiconductor substrate a first gate dielectric layer insulating the selection gate from the substrate; a vertical channel region extending in the substrate along the first gate dielectric layer; a horizontal floating gate extending above the substrate; a second gate dielectric layer insulating the horizontal floating gate from the substrate; a horizontal control gate extending above the floating gate; and an embedded layer forming a collective source plane in electrical contact with the vertical channel region, the collective source plane being configured to collect programming currents for programming the memory cell and other memory cells formed in the substrate, wherein the selection gate covers a lateral face of the floating gate, the floating gate being separated from the selection gate only by the first gate dielectric layer, and separated from the vertical channel region.
地址 Rousset FR