发明名称 Reference voltage circuit and electronic device
摘要 Provided is a reference voltage circuit capable of forming optimal circuits for various modes of an electronic device. The reference voltage circuit includes, between respective transistors forming the reference voltage circuit and between the transistors and a power supply terminal, switching elements configured to switch a circuit configuration of the reference voltage circuit.
申请公布号 US9425789(B1) 申请公布日期 2016.08.23
申请号 US201615049994 申请日期 2016.02.22
申请人 SII SEMICONDUCTOR CORPORATION 发明人 Maetani Fumihiko;Koike Toshiyuki
分类号 G05F1/10;H03K3/42;H03K17/687;G05F3/00;G11C5/14;G05F3/02 主分类号 G05F1/10
代理机构 Brinks Gilson & Lione 代理人 Brinks Gilson & Lione
主权项 1. A reference voltage circuit connected between a first power line and a second power line, the reference voltage circuit comprising: a first switching element including one terminal connected to the first power line; a first N-type depletion MOS transistor including a gate and a source connected to each other, and a drain connected to another terminal of the first switching element; a first N-type enhancement MOS transistor including a gate connected to an output terminal of the reference voltage circuit, a drain connected to the source of the first N-type depletion MOS transistor, and a source connected to the second power line; a second switching element connected between the gate of the first N-type depletion MOS transistor and the gate of the first N-type enhancement MOS transistor; a third switching element including one terminal connected to the first power line; a second N-type depletion MOS transistor including a gate connected to the gate of the first N-type depletion MOS transistor, and a drain connected to another terminal of the third switching element; a resistor circuit connected between a source of the second N-type depletion MOS transistor and the second power line; and a fourth switching element connected between the source of the second N-type depletion MOS transistor and the gate of the first N-type enhancement MOS transistor.
地址 Chiba JP