Four-phase clock generator with timing sequence self-detection

摘要

A four-phase clock generator with timing sequence self-detection including a phase-locked loop (PLL), a frequency dividing module, and a detection and control module. The PLL generates a first to a fourth reference clock signal with the same frequency, respectively, wherein each consecutive two of the first to the fourth reference clock signals have a 90-degree phase difference. The frequency dividing module is coupled to the PLL and determines whether to perform frequency dividing on the first to the fourth reference clock signals to obtain a first through a fourth output clock signal according to a first control signal. The detection and control module is coupled to the frequency dividing module and detects a timing sequence of the first to the fourth output clock signals to output the first control signal accordingly.

主权项

1. A four-phase clock generator with timing sequence self-detection, comprising:
a phase-locked loop (PLL) for generating a first to a fourth reference clock signal with a same frequency, respectively, wherein each consecutive two of said first to said fourth reference clock signals have a 90-degree phase difference; a frequency dividing module being coupled to said phase-locked loop to determine whether to perform frequency dividing on said first to said fourth reference clock signals to obtain a first through a fourth output clock signal according to a first control signal, wherein said frequency dividing module is triggered by said fourth reference clock signal to start perform frequency dividing; and a detection and control module being coupled to said frequency dividing module to detect a timing sequence of said first to said fourth output clock signals to output said first control signal accordingly; wherein when the phase difference for each consecutive two of the four reference clock signals is no longer 90-degree, said first control signal controls said frequency dividing module to stop performing frequency dividing on said first to said fourth reference clock signals since said timing sequence of said first to said fourth output clock signals is incorrect.