Clock enabling circuit

摘要

A clock enabling circuit for providing a gated clock signal in response to receiving clock request information is presented. The clock enabling circuit comprises a clock request input, a clock input, and a flip-flop stage. It also includes a first sub-circuitry comprising a first input being coupled with the clock request input and an output being coupled with the flip-flop stage for providing a set information to the flip-flop stage in response to the receipt of the clock request information, the flip-flop stage being configured to provide a clock enabling information in response to receiving the set information and a second sub-circuitry comprising a first and a second input, the first input being coupled with the clock input and the second input being coupled with the flip-flop stage, the second sub-circuitry comprising an output for providing the gated clock signal in response to receiving the clock enabling information.

主权项

1. A clock enabling circuit for providing a gated clock signal (CLK_G) in response to receiving clock request information (REQ), the clock enabling circuit comprising:
a clock request input for receiving the clock request information (REQ); a clock input for receiving a clock signal (CLK); a flip-flop stage comprising at least a first and a second flip-flop, wherein an output of the first flip-flop is coupled with the input of the second flip-flop; a first sub-circuitry comprising at least a first input being coupled with the clock request input and an output being coupled with the flip-flop stage for providing a set information (SET) to the flip-flop stage in response to receipt of the clock request information (REQ), the flip-flop stage being configured to provide a clock enabling information (CLK_EN) in response to receiving the set information (SET); a second sub-circuitry comprising a first and a second input, the first input being coupled with the clock input for receiving the clock signal (CLK) and the second input being coupled with the output of the flip-flop stage for receiving the clock enabling information (CLK_EN), the second sub-circuitry comprising a triggering circuitry for providing, based on the clock enabling information (CLK_EN), a synchronized clock enabling information (sCLK_EN) that is synchronized with an edge of the clock signal (CLK), an output of the second sub-circuitry providing the gated clock signal in response to the synchronized clock enabling information (sCLK_EN) and the clock signal (CLK).