发明名称 Current redistribution in a printed circuit board
摘要 In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.
申请公布号 US9468090(B2) 申请公布日期 2016.10.11
申请号 US201213662651 申请日期 2012.10.29
申请人 Cisco Technology, Inc. 发明人 Sabavat Goutham;Mohamed Javid;Ramanathan Subramanian;Scearce Stephen A.
分类号 H05K1/02 主分类号 H05K1/02
代理机构 Lempia Summerfield Katz LLC 代理人 Lempia Summerfield Katz LLC
主权项 1. An apparatus comprising: a signal layer of a printed circuit board; a power plane layer of the printed circuit board; and an insulating layer of the printed circuit board between the signal layer and the power plane layer, wherein the power plane layer comprises a conducting sheet having a predetermined spatial variation such that current flows in a first area with a discontinuous directional pattern formed in the conductive sheet differently than current flows in a second area with a discontinuous hatched pattern formed in the conductive sheet, and wherein the discontinuous directional pattern steers current toward a first region of the power plane, and the discontinuous hatched pattern steers current away from a vertical interconnect access of the row of vertical interconnect accesses in a second region of the power plane, wherein conductors of the direction pattern are diagonal to conductors of the discontinuous hatched pattern and the conductors of the directional pattern are diagonal to a direction of the row of the vertical interconnect access.
地址 San Jose CA US