发明名称 Low resistance semiconductor process and structures
摘要 A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.
申请公布号 US6486060(B2) 申请公布日期 2002.11.26
申请号 US19980146639 申请日期 1998.09.03
申请人 发明人
分类号 H01L21/311;H01L21/60;H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/311
代理机构 代理人
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