DISPLAY DEVICE

摘要

A substantially rectangular display panel includes a first edge extending in a first major axis direction of the rectangular shape and a second edge extending in a second major axis direction of the rectangular shape, the second direction being different from the first direction. The display panel includes: a plurality of gate lines extending in the first direction; and a gate lines driver including a plurality of main stages sequentially connected to each other and configured for outputting gate signals to the gate lines, where the plurality of stages further includes one or more dummy stages arranged in a row along the second edge and not connected to the plurality of gate lines, and where a layout arrangement of a plurality of thin film transistors included in the main stage is different from a corresponding layout arrangement of corresponding thin film transistors included in the at least one dummy stage.

主权项

1. A display panel having a first edge extending in a first direction and a second edge extending in a second direction that is different from the first direction, wherein the display panel is subdivided into a display area and a peripheral area and comprises:
a plurality of gate lines extending substantially in the second direction in the display area; and a gate driver including a plurality of main stages sequentially arranged in the first direction in the peripheral area and configured for outputting respective gate signals to respective ones of the gate lines, wherein the gate driver further includes one or more dummy stages that are not connected to the gate lines of the display area and disposed in a row area alongside the second edge, wherein the main stages arranged alongside the first edge; wherein at least one of the main stages connects to at least one dummy stage of the one or more dummy stages, wherein one of the main stages includes a first transistor including at least one first unit subtransistor connected in parallel with each other, and one of the one or more dummy stages includes a second transistor corresponding to the first transistor and including at least one second unit subtransistor connected in parallel with each other, and wherein a channel width of the first unit subtransistor is different from a channel width of the second unit subtransistor.