Wafer level light-emitting diode array

摘要

A wafer level light-emitting diode (LED) array includes: a growth substrate; a plurality of LEDs arranged over the substrate, each including a first semiconductor layer, an activation layer, and a second semiconductor layer; a plurality of upper electrodes formed from a common material and electrically connected to the first semiconductor layers of the corresponding LEDs; and first and second pads arranged over the upper electrodes. The LEDs are connected in series by the upper electrodes, the first pad is electrically connected to an input LED from among the LEDs connected in series, and the second pad is electrically connected to an output LED from among the LEDs connected in series. Accordingly, a flip chip-type LED array can be provided which can be driven with a high voltage.

主权项

1. A light emitting diode array, comprising:
a substrate; a plurality of light emitting diodes arranged over the substrate, each of the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer; a plurality of upper electrodes of a common material arranged over the plurality of light emitting diodes, each of the plurality of upper electrodes being electrically connected to the first semiconductor layer of a respective one of the light emitting diodes and insulated from the second semiconductor layer of the respective one of the light emitting diodes by a first insulating layer positioned at least partially below each of the plurality of upper layer electrodes; and first and second pads arranged over the upper electrodes, wherein at least one of the upper electrodes electrically connected to a given one of the light emitting diodes is electrically connected to the second semiconductor layer of another light emitting diode adjacent to the given light emitting diode, wherein the light emitting diodes are electrically connected in series by the upper electrodes, wherein the first pad is electrically connected to at least one of the light emitting diodes at a power input region, and wherein the second pad is electrically connected to at least one of the light emitting diodes at a power output region; and further comprising lower electrodes arranged over the second semiconductor layers of the light emitting diodes, wherein the first interlayer insulating layer is disposed partially over the lower electrodes.