Enhanced ESD protection of integrated circuit in 3DIC package

摘要

Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.

主权项

1. A device comprising:
an interposer electrically connected to a supporting substrate; a configurable and patterned array of electrostatic discharge (ESD) protection cells inside the interposer; and an integrated circuit (IC) electrically connected to the interposer comprising a hard block, the hard block being electrically connected to at least one ESD protection cell of the array of ESD protection cells.