ON-CHIP WORD LINE VOLTAGE GENERATION FOR DRAM EMBEDDED IN LOGIC PROCESS

摘要

A memory system that includes a dynamic random access memory (DRAM) cell (300), a word line (303), and a CMOS word line driver (400) fabricated using a conventional logic process. The word line driver (400) is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line (303), thereby controlling access to the DRAM cell (300). A positive boosted voltage generator (700) is provided to generate the positive boosted voltage, such that this voltage is greater then V>dd< but less than V>dd< plus the absolute value of a transistor threshold voltage V>t<. Similarly, a negative boosted voltage generator (800) is provided to generate a negative boosted voltage, such that this voltage is less than V>ss< by an amount less than V>t<. A coupling circuit (600) is provided between the word line driver (400) and one of the positive or negative boosted voltage generators (700 or 800). The coupling circuit (600) couples the word line driver (400) to the selected one of the positive or negative boosted word line generators only when the word line (303) is activated. The positive boosted voltage generator (700) includes a charge pump control circuit (1000) that limits the positive boosted voltage to a voltage less than V?dd> plus Vt. Similarly, the negative boosted voltage generator (800) includes a charge pump control circuit (1100) that limits the negative boosted voltage to a voltage greater than Vss minus Vt.