发明名称 MANUFACTURE OF CHIP-SIZED PACKAGE
摘要 PROBLEM TO BE SOLVED: To suppress to the utmost the increase in the number of masks and an increase in the man-hours in the manufacturing method of a chip-sized package, by a method wherein a barrier layer covering a metal electrode pad is formed on the side more inner than a wiring layer, and after a Cu plating is applied, an electrode only for plating is etched using the wiring layer as the mask. SOLUTION: An Al electrode pad 2 is formed on a semiconductor substrate 1, a passivation film 3 consisting of an SiN film is formed on the surface of the substrate 1 in such a way as to cover this pad 2 to provide an aperture on the pad 2, a Cr film is sputtered over the whole surface of the film 3 to make the Cr film adhere on the film 3, the Cr film is subjected to wet etching, and a barrier layer 4 is formed on the Cr film in such a way as to cover the pad 2. An electrode layer 5 for plating consisting of a Cu layer is formed on the whole surface of the layer 4 by sputtering, photoresist layers 6 are formed on prescribed regions of the electrode layer 5, a wiring layer 7 is formed to remove the layers 6, the unwanted part of the layer 5 is removed using the layer 7 as a mask, and the layer 5 is left only under the layer 7. Accordingly, a chip-sized package can be formed y a manufacturing method, wherein it is made possible to perform a processing on the layer 4 through the wet etching and an increase in the number of masks and an increase in man-hours are suppressed to the utmost.
申请公布号 JP2000183213(A) 申请公布日期 2000.06.30
申请号 JP19980351784 申请日期 1998.12.10
申请人 SANYO ELECTRIC CO LTD 发明人 TAKAO YUKIHIRO;KUBOTA TETSUYA
分类号 H01L21/3205;H01L23/12;H01L23/52 主分类号 H01L21/3205
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