发明名称 |
Semiconductor process temperature optimization |
摘要 |
A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure. |
申请公布号 |
US9349609(B2) |
申请公布日期 |
2016.05.24 |
申请号 |
US201414230065 |
申请日期 |
2014.03.31 |
申请人 |
GLOBALFOUNDRIES INC. |
发明人 |
Greene Brian J.;Liang Yue;Yu Xiaojun |
分类号 |
H01L21/324;H01L21/3205;H01L29/66 |
主分类号 |
H01L21/324 |
代理机构 |
|
代理人 |
Cai, Esq. Yuanmin |
主权项 |
1. A method comprising:
forming a structure comprising a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices; depositing a thermal optimization layer above the structure; patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from above a first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region; and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure. |
地址 |
Grand Cayman KY |