Structures and methods for monitoring dielectric reliability with through-silicon vias

摘要

Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.

主权项

1. A through-silicon via (TSV) test structure comprising:
a TSV disposed in a semiconductor substrate; and a plurality of multilevel test structures disposed adjacent to the TSV, wherein each of the plurality of multilevel test structures occupies at least two metallization levels, wherein each of the plurality of multilevel test structures comprises a stacked via-comb structure, wherein each stacked via-comb structure comprises a plurality of vias and traces configured in an electrical parallel connection, and wherein each of the plurality of stacked via-comb structures are arranged in a staggered configuration.