Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor

摘要

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

主权项

1. A method, comprising:
providing a semiconductor structure comprising a logic transistor region, a ferroelectric transistor region and an input/output transistor region; forming a first protection layer over said semiconductor structure, said first protection layer covering said logic transistor region and said input/output transistor region, at least a portion of said ferroelectric transistor region not being covered by said first protection layer; after forming said first protection layer, forming a recess in said ferroelectric transistor region by performing an etch process adapted to remove a semiconductor material of said ferroelectric transistor region; after said etch process, performing an oxidation process adapted to oxidize said semiconductor material of said ferroelectric transistor region and performing a wet etch adapted to remove an oxide formed in said oxidation process; and depositing a ferroelectric transistor dielectric over said semiconductor structure, wherein a portion of said ferroelectric transistor dielectric is deposited in said recess, removing said ferroelectric transistor dielectric and said first protection layer from said logic transistor region and said input/output transistor region, forming an input/output transistor dielectric over said input/output transistor region, and forming a logic transistor dielectric over at least said logic transistor region.