METHOD AND APPARATUS FOR IMPROVING A LOAD INDEPENDENT BUFFER

摘要

Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.

主权项

1. An apparatus comprises:
a buffer including a plurality of drivers including first and second drivers, wherein the first driver comprises:
a first transistor having a gate terminal to receive a input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first reference node;a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second reference node;a first capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; anda first switch coupled to the capacitor and operable to degrade an electrical path through the first capacitor; and wherein the second driver comprises:
a third transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to the first reference node;a fourth transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to the second reference node;a second capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; anda second switch coupled to the second capacitor and operable to degrade an electrical path through the second capacitor; and a slew rate controller electrically coupled to the buffer, wherein the slew rate controller is to control the first and second switches.