Sampling clock adjustment for an analog to digital converter of a receiver

摘要

A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.

主权项

1. A receiver comprising:
an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock; a finite impulse response filter to generate at least one filtered input signal based on the at least one digital input signal; a data decision circuit to generate recovered data based on the at least one filtered input signal; and a feedback loop coupled to receive the at least one filtered input signal and to receive the recovered data and to generate the sampling clock based on the at least one filtered input signal and the recovered data, the feedback look comprising:
a signal reconstruction circuit to generate at least one reconstructed input signal corresponding to a reconstructed version of the at least one filtered input signal based on the recovered data; anda timing error circuit to generate at least one timing error signal indicative of a difference between the at least one filtered input signal and the at least one reconstructed input signal; anda clock generator circuit to generate the sampling clock based on the at least one timing error signal.