Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

摘要

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

主权项

1. A re-programmable non-volatile semiconductor memory, comprising:
a plurality of planes stacked on top of one another over a semiconductor substrate, in each one of the planes, a plurality of word lines elongated in a x-direction and spaced apart in a y-direction across the plane; a plurality of local bit lines extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the planes between the word lines in the y-direction, the word line and the local bit lines therefore crossing adjacent each other at a plurality of crossings in the plurality of planes, wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates; a plurality of re-programmable non-volatile memory elements, each non-volatile memory element connected between a corresponding word line and corresponding local bit lines adjacent corresponding crossings, each non-volatile memory elements having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto; a plurality of select devices formed in the substrates, each select device able to connect a corresponding one of the local bit lines to a corresponding one of global bines formed in the substrate; word line select circuits for addressing one or more word line of one or more groups of the plurality of non-volatile memory elements to be reset; and a control circuit formed in the substrate to connect, wherein in response to control signals, including addresses of one or more groups of the plurality of memory elements to be reset, selected ones of the plurality of local bit lines to the plurality of global bit lines in a manner that for each global bit line at least two local bit lines adjacent to each other are connected to said global bit line at a same time, said two local bit lines connected each via a single memory element to a same corresponding selected word line.