发明名称 |
Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells |
摘要 |
This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch. Thus, a low-aspect-ratio etch can be employed to pattern P-channel devices, and a blanket P+ implant may be performed without implanting the P-type impurity into source/drain regions of the N-channel devices. Another important feature of the invention is the incorporation of P-channel gate sidewall spacers and offset P-channel implants into the process flow.
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申请公布号 |
US5494841(A) |
申请公布日期 |
1996.02.27 |
申请号 |
US19940322807 |
申请日期 |
1994.10.13 |
申请人 |
MICRON SEMICONDUCTOR, INC. |
发明人 |
DENNISON, CHARLES H.;AHMAD, AFTAB |
分类号 |
H01L27/092;H01L21/8238;H01L21/8242;H01L27/105;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 |
主分类号 |
H01L27/092 |
代理机构 |
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主权项 |
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