| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a design method for a semiconductor integrated circuit wherein irregularities of transistor characteristics and skew are reduced, and its design equipment. SOLUTION: In a design method for this semiconductor integrated circuit, a plurality of object cells wherein the irregularities of transistor characteristics in manufacturing or clock skew is to be restrained are assigned out of arbitrary cells on a chip in a cell base IC (S102). A method for searching an empty cell for arranging a dummy cell having dummy gate polysilicon is assigned (S103). A position on which a cell is not mounted is searched for with respect to the whole surface of the chip by using a CAD tool, and an empty cell is recognized (S104). Whether an empty cell exisists in the vicinity of the object cells is searched for according to the assigned method for searching for an empty cell (S105). The dummy cell is arranged in the empty cell in the vicinity of the object cells (S106).</p> |
