| 发明名称 |
PACKED WRITE COMPLETIONS |
| 摘要 |
A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes. |
| 申请公布号 |
US2016188500(A1) |
申请公布日期 |
2016.06.30 |
| 申请号 |
US201414583147 |
申请日期 |
2014.12.25 |
| 申请人 |
Intel Corporation |
发明人 |
Morris Brian S.;Swanson Jeffrey C.;Nale Bill;Blankenship Robert G.;Willey Jeff;Hendrickson Eric L. |
| 分类号 |
G06F13/16;G11C7/10 |
主分类号 |
G06F13/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
memory buffer logic to:
identify a plurality of completed writes to memory, wherein the plurality of completed writes are to correspond to a plurality of write requests from a host device received over a buffered memory interface; andsend a completion packet to the host device, wherein the completion packet is to comprise a plurality of write completions to correspond to the plurality of completed writes. |
| 地址 |
Santa Clara CA US |
