发明名称 Digital Signal Processor
摘要 A processor configured to: receive, at a floating-point-input-terminal, an input-block of data comprising a plurality of floating-point numbers each floating-point number comprising a mantissa and an exponent; determine an input-scale-factor based on a previous-input-block-exponent-value associated with a previous-input-block of data; and convert the input-block of data into a fixed-point-block of data in accordance with the input-scale-factor, wherein the fixed-point-block of data comprises a plurality of fixed-point-values that can represent the plurality of floating-point numbers within a particular range.
申请公布号 US2016188293(A1) 申请公布日期 2016.06.30
申请号 US201514964817 申请日期 2015.12.10
申请人 NXP B.V. 发明人 Barat Quesada Francisco
分类号 G06F5/01 主分类号 G06F5/01
代理机构 代理人
主权项 1. A processor configured to: receive, at a floating-point-input-terminal, an input-block of data comprising a plurality of floating-point numbers each floating-point number comprising a mantissa and an exponent; determine an input-scale-factor based on a previous-input-block-exponent-value associated with a previous-input-block of data; and convert the input-block of data into a fixed-point-block of data in accordance with the input-scale-factor, wherein the fixed-point-block of data comprises a plurality of fixed-point-values that can represent the plurality of floating-point numbers within a particular range.
地址 Eindhoven NL