Multiprocessor system and synchronous engine device thereof

摘要

The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules.

主权项

1. A synchronous engine device of multiprocessor, characterized in that the synchronous engine device includes:
a plurality of storage queues, being configured to receive synchronization primitives transmitted by a plurality of processors, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, being configured to select the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, the scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, being configured to receive the synchronization primitives transmitted by the scheduling modules to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, being configured to communicate with the virtual synchronous memory structure module to read and write the main memory of all processors and initiate an interrupt request to the processors; a configuration register, being configured to store various configuration information required by the processing modules.