| 摘要 |
In a partial display mode, a source IC outputs a start signal at an "H" level designating the start of vertical scanning by a vertical scanning circuit, over a plurality of cycles from before a time T 1 to after a time T 8 . A plurality of shift registers sequentially shift the start signal in synchronization with a clock signal to sequentially drive a plurality of activation enable signals, respectively, to an "H" level. Then, after time T 8 when first to fourth activation enable signals simultaneously attain an "H" level, the source IC outputs an enabling signal at an "H" level to the vertical scanning circuit. In response, the vertical scanning circuit simultaneously activates first to fourth gate lines corresponding to the first to the fourth activation enable signals, respectively.
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