Method and apparatus for memory command input and control

摘要

Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

主权项

1. An apparatus comprising:
a first memory unit including a first array of memory cells and control logic, the first memory unit configured to receive command information and chip select information; and a second memory unit including a second array of memory cells, the second memory unit coupled to the first memory unit, the first memory unit configured to access data stored in the first array of memory cells responsive to the command information when the chip select information designates the first memory unit, and further configured to cause the second memory unit to access data stored in the second array of memory cells responsive to the command information when the chip select information designates the second memory unit, wherein the control logic is configured to detect a deselect condition wherein the chip select information does not designate either of the first and second memory units.