发明名称 |
Dual work function buried gate type transistor and method for fabricating the same |
摘要 |
A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined in the isolation layer; a fin region formed under the first trench; and a buried gate electrode covering sidewalls of the fin region and filling the first and second trenches. The buried gate electrode includes a first work function layer formed on the sidewalls of the fin region; a second work function layer formed on sidewalls of the first trench and the second trench; a third work function layer positioned over the fin region and contacting the second work function layer; and a low resistance layer contacting the third work function layer and partially filling the first and second trenches. |
申请公布号 |
US9472646(B2) |
申请公布日期 |
2016.10.18 |
申请号 |
US201514965325 |
申请日期 |
2015.12.10 |
申请人 |
SK Hynix Inc. |
发明人 |
Oh Tae-Kyung |
分类号 |
H01L29/66;H01L29/423;H01L29/49;H01L29/06;H01L21/311;H01L21/306;H01L21/28;H01L21/3213;H01L29/78;H01L27/22;H01L27/24;H01L27/108 |
主分类号 |
H01L29/66 |
代理机构 |
IP & T Group LLP |
代理人 |
IP & T Group LLP |
主权项 |
1. A method for fabricating a transistor, comprising:
forming an isolation layer to define an active region, in a substrate; etching the isolation layer and the active region to form a trench; recessing the isolation layer in the trench to form a fin region; forming a gate dielectric layer on sidewalls of the trench and on a top surface and sidewalls of the fin region; forming a first conductive layer which lines the gate dielectric layer; selectively removing the first conductive layer to form a first work function layer on the sidewalls of the fin region and a preliminary second work function layer on the sidewalls of the trench; forming a second conductive layer over the first work function layer and the preliminary second work function layer; forming a third work function layer which fills the trench, over the second conductive layer; and recessing the third work function layer, the second conductive layer and the second work function layer to form a buried gate electrode. |
地址 |
Gyeonggi-do KR |