PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO

摘要

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

主权项

1. A circuit comprising:
(a) a serial data input; (b) a shift register clock lead carrying a shift register clock signal; (c) a plurality of scan chains, each of the scan chains including a plurality of flip flops coupled in series and having an scan input and an scan output; and (d) a shift register having a certain number of storage elements to store a certain number of data bits, an input coupled to the serial data input, a plurality of outputs coupled to the scan inputs, and a shift register clock input coupled to the shift register clock lead, in which the certain number of data bits are loaded onto the plurality of outputs after all of the certain number of data bits are shifted into the certain number of storage elements, and all of the certain number of data bits stored in the certain number of storage elements are loaded onto the plurality of outputs at once within one cycle of the shift register clock signal after a last bit of the certain number of data bits is shifted into the certain number of storage elements.