| 摘要 |
In a decode circuit comprising a decoding section for decoding an input signal in response to a controlled clock signal into an intermediate signal having a variable pattern, the decode circuit comprises a clock generator section for generating first through N-th clock signals having first through N-th phases different from one another, respectively, where N represents a positive integer which is not less than two. The first through the N-th clock signals are selectively used as the controlled signal. When the variable pattern of the intermediate signal is identical with a predetermined pattern, a coincidence detecting section supplies the detecting section with a selected one of the first through the N-th clock signals as the controlled clock signal. When the variable pattern of the intermediate signal is identical with the predetermined pattern in the coincidence detecting section, an output section allows the intermediate signal as an output signal to pass therethrough.
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