| 摘要 |
PROBLEM TO BE SOLVED: To prevent delay in output timing of reverse data. SOLUTION: Ferroelectric capacitors Q1<SB>nm</SB>, Q2<SB>nm</SB>are provided with NMOSs 7, 10, 11, 14 of which the upper electrodes can be connected with a plate line PL<SB>m</SB>and the lower electrodes can be connected with bit lines BL2<SB>m</SB>, BL4<SB>m</SB>, NMOSs 8, 9, 12, 13 of which the lower electrodes can be connected with the plate line PL<SB>m</SB>and the upper electrodes can be connected with bit lines BL1<SB>m</SB>, BL3<SB>m</SB>. COPYRIGHT: (C)2005,JPO&NCIPI
|
