| 摘要 |
A CCD shift register capable of switching between two-phase driving and three-phase driving in which crosstalk among clock signal lines is reduced and a decrease in transfer efficiency is prevented. Transfer electrodes disposed at regular intervals along a channel region are supplied with clock signals through clock signal lines. Three pairs of clock signal lines that are supplied with an in-phase clock signal at three-phase driving are disposed next to each other. One pair of odd-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other, and one pair of even-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other.
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