System and method for aligning data bits

摘要

Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

主权项

1. A method for aligning plural data bits where each data bit has an associated leading edge, the method comprising the steps of:
(a) receiving a first plurality of the plural data bits via separate input paths of a first circuit device; (b) determining which of the first plurality of data bits arrives first based on a relative time of arrival of the leading edge of each of the first plurality of data bits; (c) adjusting the input path associated with the first-to-arrive bit of the first plurality of data bits, wherein the input path is adjusted such that the leading edge of the first-to-arrive bit is received within a predetermined threshold with respect to the leading edge of each of the first plurality of data bits; (d) receiving a second plurality of data bits of the plural data bits via separate input paths of a second circuit device; (e) determining which of the second plurality of data bits arrives first based on a relative time of arrival of the leading edge of each of the second plurality of data bits; (f) adjusting the input path associated with the first-to-arrive bit of the second plurality of data bits; (g) determining, at the first circuit device, which of the first plurality of bits arrives last based on a relative time of arrival of the leading edge of each of the first plurality of data bits; (h) determining, at the second circuit device, which of the second plurality of data bits arrives last based on a relative time of arrival of the leading edge of each of the second plurality of data bits; (i) receiving at a third circuit device a third plurality of data bits wherein the third plurality of data bits comprises the last-to-arrive bit of the first plurality of data bits and the last-to-arrive bit of the second plurality of data bits; (j) determining which of the third plurality of data bits arrives first based on a relative time of arrival of the leading edge of each of the third plurality of data bits; and (k) adjusting the input path associated with the first-to-arrive bit of the third plurality of data bits.