发明名称 Vector processor having instruction set with sliding window non-linear convolutional function
摘要 A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.
申请公布号 US9363068(B2) 申请公布日期 2016.06.07
申请号 US201414168615 申请日期 2014.01.30
申请人 INTEL CORPORATION 发明人 Azadet Kameran;Williams Joseph;Yu Meng-Lin
分类号 G06F17/15;H04L5/14;H04L25/08;G06F17/50;H04B1/62;H04L1/00;H04B1/04;G06F9/30;H04L25/03;H04L27/36;H04J11/00;H04B1/525 主分类号 G06F17/15
代理机构 代理人
主权项 1. A method performed by a processor, comprising: obtaining at least one software instruction that performs at least one non-linear convolution function for a plurality of input delayed signal samples; in response to said at least one software instruction for said at least one non-linear convolution function, performing the following steps: generating a weighted sum of two or more of said input delayed signal samples, wherein said weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of said input delayed signal samples; and repeating said generating step for at least one time-shifted version of said input delayed signal samples to compute a plurality of consecutive outputs, wherein said at least one software instruction for said at least one non-linear convolution function is part of an instruction set of said processor.
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