Circuit arrangements and methods of operating the same

摘要

In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

主权项

1. A circuit arrangement comprising:
a level shifting stage coupled to a first reference voltage; a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage; a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage; an output electrode in electrical connection with the level shifting stage for providing one of a first output voltage and a second output voltage; and a feedback circuit coupled with the level shifting stage, the output electrode and a second reference voltage; wherein the first input voltage is configured to switch between a first logic state and a second logic state and the second input voltage is configured to switch between the second logic state and the first logic state; and wherein the level shifting stage is configured to generate the first output voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state and the level shifting stage is configured to generate the second output voltage when the first input voltage is in the second logic state and the second input voltage is in the first logic state; and wherein the feedback circuit is configured to maintain the first output voltage at the output electrode above a predetermined level when the first input voltage is in the first logic state and the second input voltage is in the second logic state; wherein the level shifting stage comprises a current mirror, the current mirror comprising:
a first set of sequentially coupled pull-up and pull-down sub-circuits; and a second set of sequentially coupled pull-up and pull-down sub-circuits, the second set of sequentially coupled pull-up and pull-down sub-circuits coupled to the first set of sequentially coupled pull-up and pull-down sub-circuits to form the current mirror, wherein the first set of sequentially coupled pull-up and pull-down sub-circuits comprises:
a first pull-up transistor having a control electrode, a first controlled electrode and a second controlled electrode; anda first pull-down transistor having a control electrode, a first controlled electrode and a second controlled electrode;wherein the first controlled electrode of the first pull-down transistor is coupled to the first controlled electrode of the first pull-up transistor, andwherein the control electrode of the first pull-up transistor is further coupled to the first controlled electrode of the first pull-up transistor, wherein the second set of sequentially coupled pull-up and pull-down sub-circuits comprises: a second pull-up transistor having a control electrode, a first controlled electrode and a second controlled electrode; a second pull-down transistor having a control electrode, a first controlled electrode and a second controlled electrode; and a current limiter sub-circuit having a first end and a second end;
wherein the first controlled electrode of the second pull-down transistor is coupled to the first end of the current limiter sub-circuit and the first controlled electrode of the second pull-up transistor is coupled to the second end of the current limiter sub-circuit,wherein the feedback circuit is coupled directly to the second reference voltage, andwherein the feedback circuit is coupled in series with the first pull-up transistor and the first pull-down transistor.