Apparatus and methods for leakage current reduction in integrated circuits

摘要

This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.

主权项

1. An integrated circuit comprising:
a plurality of digital logic subcircuits each having a plurality of inputs and each comprising a plurality of logic gates, wherein each of the plurality of digital logic subcircuits is configured to provide a processed signal comprising at least one bit, and wherein the plurality of digital logic subcircuits comprises a first digital logic subcircuit and a second digital logic subcircuit; a plurality of polarization circuits each configured to receive a standby signal, and wherein the plurality of polarization circuits comprises a first polarization circuit and a second polarization circuit, wherein the first polarization circuit is configured to receive a digital input signal comprising a plurality of bits and the second polarization circuit is configured to receive a portion of the at least one bit of the processed signal of a digital logic subcircuit of the plurality of digital logic subcircuits, wherein when the standby signal is deactivated, the first polarization circuit is configured to control the plurality of inputs of the first digital logic subcircuit based on the digital input signal and the at least one polarization circuit is configured to control the plurality of inputs of the second digital logic subcircuit based on the portion of the at least one bit of the processed signal of the digital logic subcircuit of the plurality of digital logic subcircuits, and wherein when the standby signal is activated the first polarization circuit is configured to control the plurality of inputs of the first digital logic subcircuit to a low power state associated with a smaller leakage current of the plurality of logic gates of the first digital logic subcircuit relative to at least one other state of the first digital logic subcircuit and the second polarization circuit is configured to control the plurality of inputs of the second digital logic subcircuit to a low power state associated with a smaller leakage current of the plurality of logic gates of the second digital logic subcircuit relative to at least one other state of the second digital logic subcircuit; and a first plurality of state elements configured to receive the processed signal from at least one digital logic subcircuit of the plurality of digital logic subcircuits; wherein the integrated circuit is configured such that the first plurality of state elements are inhibited from loading a value of the processed signal when the standby signal is activated.