发明名称 |
Method and apparatus for measuring the duty cycle of a digital signal |
摘要 |
The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
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申请公布号 |
US7333905(B2) |
申请公布日期 |
2008.02.19 |
申请号 |
US20060383570 |
申请日期 |
2006.05.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOERSTLER DAVID WILLIAM;HAILU ESKINDER;QI JIEMING |
分类号 |
G01R29/02 |
主分类号 |
G01R29/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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